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MC74HCU04A Hex Unbuffered Inverter
High-Performance Silicon-Gate CMOS
The MC74HCU04A is identical in pinout to the LS04 and the MC14069UB. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of six single-stage inverters. These inverters are well suited for use as oscillators, pulse shapers, and in many other applications requiring a high-input impedance amplifier. For digital applications, the HC04A is recommended.
Features
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14 PDIP-14 N SUFFIX CASE 646 1
* Output Drive Capability: 10 LSTTL Loads * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 2.0 to 6.0 V; 2.5 to 6.0 V in Oscillator * * * * *
14 1
MC74HCU04AN AWLYYWWG
Configurations Low Input Current: 1 mA High Noise Immunity Characteristic of CMOS Devices In Compliance With the JEDEC Standard No. 7.0 A Requirements Chip Complexity: 12 FETs or 3 Equivalent Gates Pb-Free Packages are Available
14 14 1 SOIC-14 D SUFFIX CASE 751A 1 HCU04AG AWLYWW
14 14 1 TSSOP-14 DT SUFFIX CASE 948G 1 HCU 04A ALYWG G
14 SOEIAJ-14 F SUFFIX CASE 965 1 A L, WL Y, YY W, WW G or G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package 74HCU04A ALYWG
14 1
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2006
October, 2006 - Rev. 4
1
Publication Order Number: MC74HCU04A/D
MC74HCU04A
PIN ASSIGNMENT
A1 Y1 A2 Y2 A3 Y3 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC A6 Y6 A5 Y5 A4 Y4 A1 A2 A3
LOGIC DIAGRAM
1 3 5 2 4 6 Y1 Y2 Y3
A4 A5
9 11
8 10
Y4 Y5
FUNCTION TABLE
Inputs A L H Outputs Y H L
A6
13
12
Y6
Y=A
PIN 14 = VCC PIN 7 = GND
ORDERING INFORMATION
Device MC74HCU04AN MC74HCU04ANG MC74HCU04AD MC74HCU04ADG MC74HCU04ADR2 MC74HCU04ADR2G MC74HCU04ADTR2 MC74HCU04ADTR2G MC74HCU04AFEL MC74HCU04AFELG Package PDIP-14 PDIP-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) TSSOP-14* TSSOP-14* SOEIAJ-14 SOEIAJ-14 (Pb-Free) 2000 / Tape & Reel 2500 / Tape & Reel 55 Units / Rail 25 Units / Rail Shipping
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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MC74HCU04A
I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I III I I I I I IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII II III I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I II I I I I I IIIIIIIIIIII II III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I I II I I I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIIIIIIIIIIIIIIIIIIIII III II II IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII I I I I I IIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I
IIIIIIIIIIIIIIIIIIII I I I I III III II I I I I I I I I I IIIIIIIIIIIII III I I II I I I I I I I IIIIIIIIIIIII III I I I I I IIIIIIIIIIII I II I I I I I I I IIIIIIIIIIIII III I I I III I I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I IIIIIIIIIIIII III I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I I I I IIIIIIIIIIIII III I I I I I IIIIIIIIIIIII III I I I I I I I I I IIIIIIIIIIIIIIII IIII IIIIIII I IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS
VCC Vin Iin Vout Iout PD SymbolIIIIIIIIIIIIII Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) Value Unit - 0.5 to + 7.0III V V V - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 25 50 750 500 450 DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA DC Output Current, per Pin ICC DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Plastic DIP SOIC Package TSSOP Package mW Tstg TL Storage Temperature - 65 to + 150 260 _C _C Lead Temperature, 1 mm from case for 10 Seconds Plastic DIP, SOIC or TSSOP Package
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Derating -- Plastic DIP: -10mW/_C from 65_ to 125_C SOIC Package: -7mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol VCC TA Parameter DC Supply Voltage (Referenced to GND)
Min 2.0 0
Max 6.0
Unit V V
Vin, Vout tr, tf
DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1)
VCC
- 55 -
+ 125 No Limit
_C ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit v 85_C 1.7 2.5 3.6 4.8 0.3 0.5 0.8 1.1 1.8 4.0 5.5
Symbol VIH
Parameter
Test Conditions
VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0
- 55 to 25_C 1.7 2.5 3.6 4.8 0.3 0.5 0.8 1.1 1.8 4.0 5.5
v 125_C l.7 2.5 3.6 4.8
Unit V
Minimum High-Level Input Voltage
Vout = 0.5 V* |Iout| v 20 mA
VIL
Maximum Low-Level Input Voltage
Vout = VCC - 0.5 V* |Iout| v 20 mA
0.3 0.5 0.8 1.1 1.8 4.0 5.5
V
VOH
Minimum High-Level Output Voltage
Vin = GND |Iout| v 20 mA Vin = GND
V
|Iout| v 2.4 mA |Iout| v 4.0 mA |Iout| v 5.2 mA
2.36 3.86 5.36
2.26 3.76 5.26
2.20 3.70 5.20
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MC74HCU04A
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II I I III I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIII III I I I I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIII III I I I I I I IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII II I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I IIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit v 85_C 0.2 0.5 0.5 Symbol VOL Parameter Test Conditions VCC V 2.0 4.5 6.0 3.0 4.5 6.0 6.0 6.0 - 55 to 25_C 0.2 0.5 0.5 v 125_C 0.2 0.5 0.5 Unit V Maximum Low-Level Output Voltage Vin = VCC |Iout| v 20 mA Vin = VCC |Iout| v 2.4 mA |Iout| v 4.0 mA |Iout| v 5.2 mA 0.32 0.32 0.32 0.32 0.37 0.37 0.32 0.40 0.40 Iin Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Vin = VCC or GND Iout = 0 mA 0.1 1 1.0 10 1.0 40 mA mA ICC 1. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). 2. For VCC = 2.0 V, Vout = 0.2 V or VCC - 0.2 V.
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit v 85_C 90 45 18 15 95 32 19 16 10
Symbol tPLH, tPHL
Parameter
VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 --
- 55 to 25_C 70 40 14 12 75 27 15 13 10
v 125_C 105 50 21 18 110 36 22 19 10
Unit ns
Maximum Propagation Delay, Input A to Output Y (Figures 1 and 2)
tTLH, tTHL
Maximum Output Transition Time, Any Output (Figures 1 and 2)
ns
Cin
Maximum Input Capacitance
pF
3. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). 4. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V 15
2f
CPD
Power Dissipation Capacitance (Per Inverter)*
pF
5. Used to determine the no-load dynamic power consumption: P D = CPD VCC ON Semiconductor High-Speed CMOS Data Book (DL129/D).
+ ICC VCC . For load considerations, see Chapter 2 of the
VCC
TEST POINT tr INPUT A 90% 50% 10% tPHL OUTPUT Y tTHL 90% 50% 10% tTLH *Includes all probe and jig capacitance tf VCC GND tPLH DEVICE UNDER TEST OUTPUT CL* A Y
Figure 1. Switching Waveforms
Figure 2. Test Circuit
Figure 3. Logic Detail (1/6 of Device Shown)
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MC74HCU04A
TYPICAL APPLICATIONS
R2 R2 > > R1 C1 < C2 R1 C C1 Vout C2 R2 R1 1/6 HCU04A 1/6 HCU04A 1/6 HCU04A Vout
1/6 HCU04A
Figure 4. Crystal Oscillator
Figure 5. Stable RC Oscillator
VCC R2 INPUT 1M 1 M 1/6 HCU04A 1/6 HCU04A R2 > 6R1 Vout OUTPUT
Vin
R1
1/6 HCU04A
Figure 6. Schmitt Trigger
Figure 7. High Input Impedance Single-Stage Amplifier with a 2 to 6 V Supply Range
+V VCC
1/6 HCU04A 1/6 HCU04A INPUT 1/6 HCU04A 1/6 HCU04A OUTPUT For reduced power supply current, use high-efficiency LEDs such as the Hewlett-Packard HLMP series or equivalent.
Figure 8. Multi-Stage Amplifier
Figure 9. LED Driver
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MC74HCU04A
PACKAGE DIMENSIONS
PDIP-14 CASE 646-06 ISSUE P
14
8
B
1 7
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10 _ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10 _ 0.38 1.01
A F N -T-
SEATING PLANE
L C
H
G
D 14 PL
K
M
J M
DIM A B C D F G H J K L M N
0.13 (0.005)
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MC74HCU04A
PACKAGE DIMENSIONS
SOIC-14 CASE 751A-03 ISSUE H
-A-
14 8
-B-
P 7 PL 0.25 (0.010)
M
B
M
1
7
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
G C -T-
SEATING PLANE
R X 45 _
F
D 14 PL 0.25 (0.010)
M
K TB
S
M A
S
J
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04 1 0.58
14X
14X
1.52
1.27 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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MC74HCU04A
PACKAGE DIMENSIONS
TSSOP-14 CASE 948G-01 ISSUE B
14X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V N
S
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K
0.15 (0.006) T U
S
J J1
SECTION N-N
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
SOLDERING FOOTPRINT*
7.06 1
0.36
14X
14X
1.26
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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8
EEE CCC EEE CCC CCC
A -V-
K1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C --- 1.20 --- 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 -W- K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_
0.65 PITCH
DIMENSIONS: MILLIMETERS
MC74HCU04A
PACKAGE DIMENSIONS
SOEIAJ-14 CASE 965-01 ISSUE A
14
8
LE Q1 E HE M_ L DETAIL P
1
7
Z D e A VIEW P
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 1.42 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.004 0.008 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.056
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC74HCU04A/D

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